Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Many modern computing systems utilize multi-core processors having two or more processor cores interfaced for enhanced performance and efficient processing of multiple tasks and threads. Thread migration can be utilized in multi-core processors to mitigate issues such as thermal hotspots, cache utilization, load balancing, communication localization, and hardware error tolerance. For example, the execution of a thread may be moved away from a processing core that develops a thermal hotspot during operation. In another example, thread migration is used to move execution of a thread closer to data that the processor accesses for execution of the thread.
In some examples, when execution of a thread is migrated from a source core to a target core of a multi-core processor, the entire architectural state and micro-architectural state of the source core can be proactively migrated to the target core either through a network message or through data cache coherence operations. For example, registers and translation lookaside buffer (TLB) entries may be stored in data cache of the source core and may be subsequently migrated to data cache of the target core before being transferred to the corresponding registers and TLB of the target core. In other examples, such values may be stored on on-chip memory such as SRAM. In certain processors, additional machine instructions are executed in both the source core and the target core to achieve this migration of registers and the TLB entries. For example, additional micro-code instructions may be executed in the source core to save the architectural states and the micro-architectural states to data caches. Moreover, micro-code instructions may be executed in the target core to load these values to the corresponding registers and TLB of the target core.